Περιγραφή Μαθήματος
Section 1
Karnaugh map with entered variables, Sequential machines, FSMs with complex transition conditions, Setup and hold time, Metastability, Hazard free circuits, Asynchronous inputs to synchronous circuits, Clock skew.
Section 2
Digital systems architecture, Data paths, Register Transfer Level (RTL), Microoperations, Bus techniques, Arithmetic Logic Unit (ALU), Register file, Timing issues, Pipelining.
Section 3
Control unit of digital systems, Algorithmic State Machines (ASM), Hardwired control, Control unit design methods, Single cycle architecture, Multi cycle architecture, Control units of programmable systems, Performance increase techniques: pipeline, hazards.
Section 4
Circuit design with VHDL Design flow, Code structure, Data types, Operators and Attributes, Concurrent code, Sequential code, Signals and Variables, State machines, Designs of typical circuits, Practice on ISE Xilinx, description of circuits, simulation, synthesis.
Section 5
System design with VHDL, Packages and Components, Functions and Procedures, Design of typical systems, Creation and use of Test-benches for design verification
Στοιχεία Μαθήματος
Κωδικός μαθήματος: ΗΦY 202
Μάθημα: Μαθήματα Κορμού
Εξάμηνο: Δεύτερο Εξάμηνο
Ώρες / εβδομάδα: 2
Πιστ. Μονάδες (ECTS): 6
Διδάσκοντες: Σ. Νικολαΐδης, Β. Παυλίδης